View ML7204-001_737181.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

oki semiconductor fedl7204-001digest-01 issue date: aug. 12, 2004 ML7204-001 voip codec 1/42 general description the ML7204-001 is a speech code c for voip. as a speech codec, this lsi allows selection of g.729.a/g711 an d supports the plc (packet loss concealment) function. with an echo canceler that handles 32 ms-delay and fsk detection/generation, dtmf detection/generation, and tone detection/generation functions, the ML7204-001 is the most suitable lsi for adding the voip function to tas and routers. features ? power supply voltage digital power supply voltage (dvdd0, 1, 2): 3.0 to 3.6 v analog power supply voltage (avdd): 3.0 to 3.6 v ? speech codec: g.729.a (8 kbps)/g.711 (64 kbps) -law and a-law (supports individual setting for transmission and reception) supports itu-t g.711 appendix 1 compliant plc (packet loss concealment) function supports the 2-channel processing function (for 3-way communication) ? built-in fifo buffer (640 bytes) for transmission/reception data transfer allows selection of fr ame/dma (slave) interface ? echo canceler for handling 32 ms delay ? dtmf detection ? dtmf generation (the tone generation func tion enables generation of dtmf signals) ? tone detection: 2 types (1650 hz and 2100 hz: detection frequency can be changed) ? tone generation: 2 types ? fsk detection ? fsk generation ? built-in 16-bit timer: 1 channel ? dial pulse detection function (secondary function of general-purpose i/o ports) ? dial pulse transmission function (secondary function of general-purpose i/o ports) ? general-purpose i/o ports 64-pin package: equipped with 7 ports (with some of them having secondary function allocation) 100-pin package: equipped with 21 ports (with some of them having secondary function allocation) ? two types of built-in linear pcm codec (codec_a and codec_b) ? analog interface codec_a side: incorporates one type each of input amplifier and output amplifier (10 k ? driving) codec_b side: incorporates one type each of input amplifier and output amplifier (10 k ? driving) ? pcm interface coding format: allows selection of 16-bit linear/g.711 (64 kbps) -law or a-law ? pcm serial transmission rate: 64 khz to 2.048 mhz (fixed to 2.048 mhz for output) ? pcm time slot assignment function (allows up to 2 slots for input and 1 slot for output individually) when set to -law/a-law: supports up to 32 slots (bclk: 2.048 mhz) when set to 16-bit linear: supports up to 16 slots (bclk: 2.048 mhz)
fedl7204-001digest-01 oki semiconductor ML7204-001 2/42 ? master clock frequency: 12.288 mhz (crystal; external input) ? supports hardware and software power down ? package: 64-pin plastic qfp (qfp64-p-1414-0.80-bk) (ML7204-001ga) 100-pin plastic tqfp (tqfp100-p-1414-0.50-bk) (ml7204v-001tb)
fedl7204-001digest-01 oki semiconductor ML7204-001 3/42 block diagram txgaina rxgainb vfro0 10k ? amp2 a in0n gsx0 10k ? a in0p a mp0 linear pcm codec (codec_a) d/a0 lpf a /d0 bpf stgaina rxgain vfro1 10k ? amp3 a in1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a /d1 bpf stgainb txgainb txdet a power dvdd2 dgnd2 a gnd dvdd1 dgnd1 dvdd0 dgnd0 a vdd vregout vgb vref a vref sync(8khz) osc 12.288mhz pll xi xo ckgn mck txdetb echo cancelle r + - af lpad gpad atts attr center clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 various generator paths dtmf _ rec dtmf_code[3:0] dtmf_det fsk _ det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txdeta txdetb tone _ det0 tone0_det tone _ det1 tone1_det rxdet txgain _ s txgen sc_txen pcm i/f ts cont p/s s/p pcm codec encode r g.711 decoder g.711 rxgain_its2 rxgain_its1 pcm_txen1 txgain_pcm1 rx_sig pcm_txen0 txgain _pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm rxen0 rx_sig rxdet rxgain_sc sc_rxen mgen_e xflag tx buffer0 bus control unit tx buffer1 intb/ gpioa [ 6 ] 8b 16b frame/dma controlle r control re g iste r int rx buffe r 0 rx buffer1 rxgain _ch1 s p eech codec g.729. a g.711 encoder t s w ch2 g.711 tsw g.729. a decode r rxgain _ ch2 rx1tx2 _gain rx2tx1 _gain rxgenb rxgena various detector paths tone_gen1 (tone c/ d) fsk _ gen tone_gen0 (tone a/ b) tgen1_exfl tgen0_exfl fgen_flag rxgen txgen rxgen a rxgenb rxgena_en rxgenb_en rxgen lpen1 mgen_frfla gpioc [ 7:0 ] gpio [ 5:0 ] gpio [ 3:0 ] 4 6 8 a0-a7 d0-d15 csb rdb wrb fr0b fr1b sync clksel bclk pcmo pcmi ack0b/ gpioa[4] ack1b/ gpioa [ 5 ] dpgen dpdet gpio0 gpio2 dp det timer fdet_fer/fdet_oer dtmf_det tone0 det tone1_det dp det dtmf co de [3 : 0] fdet_rq fgen flag timovf timovf tst1 tst0 pdnb clkout txgain _ch1 txgain _ch2 note: the i/o pins represented by ? ? can be used for 100-pin packages only. dc en dc_en ch2 ch1 ch1
fedl7204-001digest-01 oki semiconductor ML7204-001 4/42 pin configuration (top view) 49 a vref vfro0 vfro1 a vdd 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dgnd0 dgnd1 vbg vregout tst1 tst0 pcmo pcmi bclk sync dvdd1 rdb wrb csb fr0b fr1b dvdd0 a0 a1 a2 a3 a4 a5 a6 a7 dgnd2 xi xo dvdd2 gpioa[0]/dpi gpioa[1] gpioa[2]/dpo gpioa[3] pdnb intb/gpioa[6] ack0b/gpioa[4] ack1b/gpioa[5] clksel a in1n gsx1 a in0p a in0n gsx0 a gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-pin plastic qfp
fedl7204-001digest-01 oki semiconductor ML7204-001 5/42 76 a vref vfro0 vfro1 a vdd 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 dgnd1 vbg v regout dgnd2 dvdd2 gpioa[0]/dpi gpioa[1] gpioa[2]/dpo gpioa[3] pdnb clksel a in1n gsx1 a in0p a in0n gsx0 a gnd rdb wrb csb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dgnd0 25 51 52 53 54 55 56 57 58 59 92 94 93 95 96 97 98 99 100 34 33 32 31 30 29 28 27 26 nc nc xi xo nc nc nc nc nc nc nc nc nc nc nc nc nc nc gpiob[0] gpiob[1] gpiob[2] gpiob[3] gpiob[4] gpiob[5] nc tst1 tst0 pcmo pcmi bclk sync fr0b fr1b dvdd0 intb/gpioa[6] a ck0b/gpioa[4] a ck1b/gpioa[5] gpioc[0] gpioc[1] gpioc[2] gpioc[3] gpioc[4] gpioc[5] gpioc[6] gpioc[7] : provided for 100-pin packages only clkout nc nc a0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 dvdd1 nc 100-pin plastic tqfp
fedl7204-001digest-01 oki semiconductor ML7204-001 6/42 pin descriptions pin tqfp100 qfp64 symbol i/o when pdnb = ?0? description 1 ? clkout o ?l? 12.288 mhz clock output 2 1 tst1 i ?0? test control input 1: normally, input ?0?. 3 2 tst0 i ?0? test control input 0: normally, input ?0?. 4 ? gpioc[0] i/o i general-purpose i/o port c [0] 5 ? gpioc[1] i/o i general-purpose i/o port c [1] 6 3 pcmo o ?hi-z? pcm data out put [open drain output pin] 7 4 pcmi i i pcm data input i clksel = ?0? pcm shift clock input 8 5 bclk i/o ?l? clksel = ?1? pcm shift clock output i clksel = ?0? pcm synchronous signal 8 khz input 9 6 sync i/o ?l? clksel = ?1? pcm synchronous signal 8 khz output 10 ? gpioc[2] i/o i general-purpose i/o port c[2] 11 ? gpioc[3] i/o i general-purpose i/o port c[3] 12 7 dvdd0 ? ? digital power supply 13 ? gpioc[4] i/o i general-purpose i/o port c[4] 14 ? gpioc[5] i/o i general-purpose i/o port c[5] 15 8 ack0b/gpioa[ 4] i/o i transmit buffer dma access acknowledge signal input (primary function) general-purpose i/o port a[4] (secondary function) [5 v tolerant pin] 16 9 ack1b/gpioa[ 5] i/o i receive buffer dma access acknowledge signal input (primary function) general-purpose i/o port a [5] (secondary function) [5 v tolerant pin] 17 ? gpioc[6] i/o i general-purpose i/o port c [6] 18 ? gpioc[7] i/o i general-purpose i/o port c [7] 19 10 fr0b (dmarq0b) o ?h? fr0b:(fd_sel = ?0?) transmit buffer frame signal output dmarq0b: (fd_sel = ?1?) transmit buffer dma access request signal 20 11 fr1b (dmarq1b) o ?h? fr1b: (fd_sel = ?0?) receive buffer frame signal output dmarq1b: (fd_sel = ?1?) receive buffer dma access request signal output 21 12 intb/gpioa[6] i/o ?h? interrupt request output (primary function) general-purpose i/o port a [6] (secondary function) [5 v tolerant pin] 22 13 csb i i chip select control input 23 14 rdb i i read control input 24 15 wrb i i write control input 25 16 dgnd0 ? ? digital ground (0.0 v)
fedl7204-001digest-01 oki semiconductor ML7204-001 7/42 pin tqfp100 qfp64 symbol i/o when pdnb = ?0? description 26 ? nc ? ? (unused) 27 17 d0 i/o i data input-output 28 18 d1 i/o i data input-output 29 ? nc ? ? (unused) 30 19 d2 i/o i data input-output 31 20 d3 i/o i data input-output 32 ? nc ? ? (unused) 33 21 d4 i/o i data input-output 34 22 d5 i/o i data input-output 35 ? nc ? ? (unused) 36 23 d6 i/o i data input-output 37 24 d7 i/o i data input-output 38 ? nc ? ? (unused) 39 25 d8 i/o i data input-output. fix the input to ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 40 26 d9 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 41 ? nc ? ? (unused) 42 27 d10 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 43 28 d11 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 44 ? nc ? ? (unused) 45 29 d12 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 46 30 d13 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 47 ? nc ? ? (unused) 48 31 d14 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 49 32 d15 i/o i data input-output. fix the input ?l? or ?h? when using the pin in 8-bit bus access (bw_sel = ?1?). 50 ? nc ? ? (unused) 51 ? nc ? ? (unused) 52 33 dvdd1 ? ? digital power supply 53 34 a0 i i address input 54 35 a1 i i address input 55 36 a2 i i address input 56 37 a3 i i address input 57 38 a4 i i address input 58 39 a5 i i address input 59 40 a6 i i address input 60 41 a7 i i address input
fedl7204-001digest-01 oki semiconductor ML7204-001 8/42 pin tqfp100 qfp64 symbol i/o when pdnb = ?0? description 61 42 pdnb i ?0? power-down input ?0?: power-down reset ?1?: normal operation 62 ? gpiob[0] i/o i general-purpose i/o port b[0] 63 ? gpiob[1] i/o i general-purpose i/o port b[1] 64 43 clksel i i sync/bclk input-output control input ?0?: sync/bclk are configured to be input ?1?: sync/bclk are configured to be output 65 ? gpiob[2] i/o i general-purpose i/o port b[2] 66 ? gpiob[3] i/o i general-purpose i/o port b[3] 67 44 dgnd1 ? ? digital ground (0.0 v) 68 ? gpiob[4] i/o i general-purpose i/o port b[4] 69 ? gpiob[5] i/o i general-purpose i/o port b[5] 70 45 gpioa[0]/dpi i/o i general-purpose i/o port a[0] [5 v tolerant pin] secondary function: input pin for dial pulse detection 71 46 gpioa[1] i/o i general-purpose i/o port a[1] [5 v tolerant pin] 72 ? nc ? ? (unused) 73 ? nc ? ? (unused) 74 47 gpioa[2]/dp o i/o i general-purpose i/o port a[2] [5 v tolerant pin] secondary function: output pin for dial pulse transmission 75 48 gpioa[3] i/o i general-purpose i/o port a[3] [5 v tolerant pin] 76 49 avdd ? ? analog power supply 77 ? nc ? ? (unused) 78 50 ain0p i i amp0 non-inverting input 79 51 ain0n i i amp0 inverted input 80 52 gsx0 o ?hi-z? amp0 output (10 k ? driving) 81 ? nc ? ? (unused) 82 53 gsx1 o ?hi-z? amp1 output (10 k ? driving) 83 54 ain1n i i amp1 inverted input 84 ? nc ? ? (unused) 85 55 avref o ?l? analog signal ground (1.4 v) 86 56 vfro0 o ?hi-z? amp2 output (10 k ? driving) 87 57 vfro1 o ?hi-z? amp3 output (10 k ? driving) 88 58 agnd ? ? analog ground (0.0 v) 89 ? nc ? ? (unused) 90 ? nc ? ? (unused) 91 59 dgnd2 ? ? digital ground (0.0 v) 92 60 xi i i 12.288 mhz crystal interface, 12.288 mhz clock input 93 ? nc ? ? (unused) 94 61 xo o ?h? 12.288 mhz crystal interface
fedl7204-001digest-01 oki semiconductor ML7204-001 9/42 pin tqfp100 qfp64 symbol i/o when pdnb = ?0? description 95 62 dvdd2 ? ? digital power supply 96 ? nc ? ? (unused) 97 ? nc ? ? (unused) 98 63 vregout ? ? internal regulator voltage output pin (approx. 2.5 v) 99 64 vbg ? ? internal regulator reference voltage output pin 100 ? nc ? ? (unused)
fedl7204-001digest-01 oki semiconductor ML7204-001 10/42 absolute maximum ratings parameter symbol condition rating unit analog power supply voltage avdd ? ?0.3 to +4.6 v digital power supply voltage dvdd ? ?0.3 to +4.6 v analog input voltage vain a nalog pin ?0.3 to avdd+0.3 v vdin1 normal digital pin ?0.3 to dvdd+0.3 v dvdd = 3.0 to 3.6 v ?0.3 to +6.0 v digital input voltage vdin2 5 v tolerant pin dvdd < 3.0 v ?0.3 to dvdd+0.3 v output current io ? ?20 to +20 ma power dissipation pd ta = 60 c, per package 350 mw storage temperature tstg ? ?65 to +150 c recommended operating conditions (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit analog power supply voltage avdd ? 3.0 3.3 3.6 v digital power supply voltage dvdd ? 3.0 3.3 3.6 v operating temperature range ta ? ?20 ? 60 c vih1 normal digital pin 0.75 dvdd ? dvdd+ 0.3 v digital high-level input voltage vih2 5 v tolerant pin 0.75 dvdd ? 5.5 v digital low-level input voltage vil digital pin ?0.3 ? 0.19 dvdd v digital input rise time tir digital pin ? 2 20 ns digital input fall time tif digital pin ? 2 20 ns digital output load capacitance cdl digital pin ? ? 50 pf digital output load resistance rdl pull-up resistance, pcmo 500 ? ? ? avref bypass capacitor cvref betw een avref-agnd 2.2+0.1 ? 4.7+0.1 f vregout bypass capacitor cvout between vregout-dgnd ? 10+0.1 ? f vbg bypass capacitor cvbg between vbg-dgnd ? 150 ? pf master clock frequency fmck mck ?0.01% 12.288 +0.01% mhz pcm shift clock frequency fbclk bclk (at input) 64 ? 2048 khz pcm synchronous signal frequency fsync sync (at input) ? 8.0 ? khz clock duty ratio drclk mck, bclk (at input) 40 50 60 % tbs bclk to sync (at input) 100 ? ? ns pcm synchronous timing tsb sync to bclk (at input) 100 ? ? ns pcm synchronous signal width tws sync (at input) 1bclk ? 100 s (note) on power-on/shut-down sequence for the analog power supply voltage (avdd) and the digital power supply voltage (dvdd) to be supplied to this lsi, it is recommended that power be applied to them simultaneously. however, if simultaneous power-up is difficult due to the power supply circuit conf iguration, power them up in the order of dvdd avdd. the power supplies should be shut down in the reverse order of power-on sequence.
fedl7204-001digest-01 oki semiconductor ML7204-001 11/42 electrical characteristics dc characteristics (avdd = 3.0 to 3.6v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit iss standby state (pdnb = ?0?, dvdd = avdd=3.3 v, ta = 25 c) ? 200 500 a idd1 operating status 1 speech codec activated/pcm i/f not used sc_en = ?1?, afea_en = ?0?, afeb_en = ?1?, xi, xo: 12.288 mhz crystal connected ? 45 55 ma power supply current idd2 operating status 2 speech codec activated/pcm i/f used sc_en = ?1?,pcmi1_en = ?1?, pcmo1_en = ?1?, afea_en=?0?, afeb_en=?0? xi, xo: 12.288 mhz crystal connected ? 50 65 ma iih vin = dvdd ? 0.01 10 a digital input pin input leakage current iil vin = dgnd ?10 ?0.01 ? a iozh vou = dvdd ? 0.01 10 a digital i/o pin output leakage current iozl vout = dgnd ?10 ? ? a high-level output voltage voh digital input pins, i/o pin ioh = 4.0 ma ioh = 0.5 ma (xo pin) ioh = 1 2.0 ma (clkout pin) 0.78 dvdd ? ? v vol1 digital output pins, i/o pin iol = ?4.0 ma iol = ?0.5 ma (xo pin) io = ?12.0 ma (clkout pin) ? ? 0.4 v low-level output voltage vol2 open drain output pins iol = ?12.0 ma ? ? 0.4 v cin1 input pins ? 6 ? pf input capacitance (*1) cin2 i/o pins ? 10 ? pf *1 design guaranteed value
fedl7204-001digest-01 oki semiconductor ML7204-001 12/42 analog interface (avdd = 3.0 to 3.6 v, dvdd0, 1 ,2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol conditio n min. typ. max. unit input resistance (*1) rin ai n0n, ain0p, ain1n 10 ? ? m ? output load resistance rl gsx0 , gsx1, vfro0, vfro1 10 ? ? k ? output load capacitance cl analog output pins ? ? 50 pf offset voltage vof vfro 0, vfro1 ?40 ? 40 mv output voltage level (*2) vo gsx0, gsx1, vfro0, vfro1 rl = 10k ? , amp input 1.3 vpp 1.158 1.3 1.458 vpp *1 design guaranteed value *2 ?7.7 dbm (600 ? ) = 0 dbm0, +3.17 dbm0 = 1.3 vpp
fedl7204-001digest-01 oki semiconductor ML7204-001 13/42 ac characteristics in speech codec = g.711 ( -law) mode (avdd = 3.0 to 3.6v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) condition parameter symbol frequency (hz) level (dbm0) min. typ. max. unit lt1 0 to 60 25 ? ? db lt2 300 to 3000 ?0.15 ? 0.20 db lt3 1020 reference ? lt4 3300 ?0.15 ? 0.80 db lt5 3400 0 ? 0.80 db transmit frequency characteristics lt6 3968.75 0 13 ? ? db lr2 0 to 3000 ?0.15 ? 0.20 db lr3 1020 reference ? lr4 3300 ?0.15 ? 0.80 db lr5 3400 0 ? 0.80 db receive frequency characteristics lr6 3968.75 0 13 ? ? db sdt1 3 35 ? ? dbp sdt2 0 35 ? ? dbp sdt3 ?30 35 ? ? dbp sdt4 ?40 28 ? ? dbp transmit signal-to-noise ratio (*1) sdt5 1020 ?45 23 ? ? dbp sdr1 3 35 ? ? dbp sdr2 0 35 ? ? dbp sdr3 ?30 35 ? ? dbp sdr4 ?40 28 ? ? dbp receive signal-to-noise ratio (*1) sdr5 1020 ?45 23 ? ? dbp gtt1 3 ?0.2 ? 0.2 db gtt2 ?10 reference ? gtt3 ?40 ?0.2 ? 0.2 db gtt4 ?50 ?0.6 ? 0.6 db transmit inter-level loss errors gtt5 1020 ?55 ?1.2 ? 1.2 db gtr1 3 ?0.2 ? 0.2 db gtr2 ?10 reference ? gtr3 ?40 ?0.2 ? 0.2 db gtr4 ?50 ?0.6 ? 0.6 db receive inter-level loss errors gtr5 1020 ?55 ?1.2 ? 1.2 db nidlt ? analog input = avref ? ? ?70 dbm0p idle channel noise (*1) nidlr ? pcmi = ?1? ? ? ?70 dbm0p transmit absolute level (*2) avt 1020 0 0.285 0.320 0.359 vrms receive absolute level (*2) avr 1020 0 0.285 0.320 0.359 vrms *1 p-message weighted filter used *2 0.320 vrms = 0 dbm0 = ?7.7 dbm (600 ? )
fedl7204-001digest-01 oki semiconductor ML7204-001 14/42 ac characteristics (gain setting) in speech codec = g.711 ( -law) mode (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit transmit/receive gain setting accuracy gac for all gain set values ?1.0 ? 1.0 db ac characteristics (tone output) in speech codec = g.711 ( -law) mode (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit frequency deviation fdft for all frequency set values ?1.5 ? 1.5 % output level olev for all gain set values ?2.0 ? 2.0 db ac characteristics (dtmf detector and ot her detectors) in sp eech codec = g.711 ( -law) mode (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit detection level accuracy dlac for all detection level set values ?2.5 ? 2.5 db ac characteristics (echo canceler) (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit echo attenuation eres ? ? 35 ? db erasable echo delay time tect ? ? ? 32 ms measuring method sin sout delay white noise generator rout rin att e.r.l (echo return loss) echo delay time echo canceler lpf 5khz level meter
fedl7204-001digest-01 oki semiconductor ML7204-001 15/42 timings of pdnb, xo, and avref (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit power-down signal pulse width tpdnb pdnb pin 250 ? ? s avdd supply delay time tavddon ? 0 ? ? ns oscillation activation time txtal ? ? ? 20 ms avref = 1.4 (90%) c5 = 4.7 f, c6 = 0.1 f (see figure 9) ? ? 600 ms avref rise time tavref avref = 1.4 (90%) c5 = 2.2 f, c6 = 0.1 f (see figure 9) ? ? 300 ms figure 1 timings of pdnb, xo, and avref (note) the capacitance of the avref capacitor (c5) affects th e avref rise time and analog characteristics. if weight is given to the analog characteristics, specify 4.7 f, and if it is given to the avref rise time, specify 2.2 f. the electrical characteristics for the analog char acteristics that are described above are guaranteed in both capacitances. pdnb 0 v dvdd t pdnb dvdd avdd 0 v dvdd avdd vregout 0 v approx. 2.5v t avddon avref approx. 1.4 v xo 0 v avdd txtal 0 v t avref 90% dvdd avdd 90%
fedl7204-001digest-01 oki semiconductor ML7204-001 16/42 pcm interface (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol conditio n min. typ. max. unit bit clock frequency fbclk cdl = 20 pf (during output) ?0.1% 2.048 +0.1% mhz bit clock duty ratio dbclk cdl = 20 pf (during output) 45 50 55 % synchronous signal frequency fsync cdl = 20 pf (during output) ?0.1% 8 +0.1% khz synchronous signal duty ratio dsync 1 cdl = 20 pf (during output) bclk = 2.048 mhz at output 45 50 55 % tbs bclk to sync (during output) 100 ? ? ns transmit/receive synchronous timing tsb sync to bclk (during output) 100 ? ? ns input setup time tds 50 ? ? ns input hold time tdh pcmi pin 50 ? ? ns tsdx ? ? 100 ns digital output delay time txd1 ? ? 100 ns txd2 ? ? 100 ns digital output hold time txd3 pcmo pin pull-up resistance rdl = 500 ? cdl = 50 pf ? ? 100 ns 01 msb lsb tws tds tdh bclk sync pcmi tbs tsb 2 3 4 5 6 7 8 - 16 g.711 lsb 16-bit linear figure 2 pcm interface input timing (long frame) 01 tws tds tdh bclk sync pcmi tbs tsb 2 3 4 5 6 7 8 9 - msb lsb g.711 17 lsb 16-bit linear figure 3 pcm interface input timing (short frame)
fedl7204-001digest-01 oki semiconductor ML7204-001 17/42 lsb tws bclk sync pcmo tbs tsb msb tsdx txd2 txd3 g.711 lsb txd3 16-bit linear 01 2 3 4 5 6 7 8 9 - 17 txd1 figure 4 pcm interface output timing (long frame) lsb tws bclk sync pcmo tbs tsb msb txd1 txd2 txd3 g.711 lsb 16-bit linear txd3 01 2 3 4 5 6 7 8 9 10 - 18 figure 5 pcm interface output timing (short frame)
fedl7204-001digest-01 oki semiconductor ML7204-001 18/42 control register interface (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta= ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit address setup time (at read) tras 10 ? ? ns address hold time (at read)) trah 0 ? ? ns address setup time (at write) twas 10 ? ? ns address hold time (at write) twah 10 ? ? ns write data setup time twds 20 ? ? ns write data hold time twdh 10 ? ? ns csb setup time (at read) trcs 10 ? ? ns csb hold time (at read) trch 0 ? ? ns csb setup time (at write) twcs 10 ? ? ns csb hold time (at write) twch 10 ? ? ns wrb pulse width tww 10 ? ? ns read data output delay time trdd ? ? 20 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 25 ? ? ns csb disable time tcd cl = 50 pf 10 ? ? ns figure 6 control register interface a7-a0 input d7-d0 input- output csb input wrb input rdb input write timing read timing twas twah twds twdh twch trdd trcs trdh tww trw a1 d1 input a2 d2 output twcs trch tras trah tcd
fedl7204-001digest-01 oki semiconductor ML7204-001 19/42 transmit/receive buffer interface (frame mode) (avdd = 3.0 to 3.6 v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit fr1b setup time tf1s 3 ? ? ns fr1b output delay time tf1d ? ? 20 ns address setup time (at read) tras 10 ? ? ns address hold time (at read)) trah 0 ? ? ns address setup time (at write) twas 10 ? ? ns address hold time (at write) twah 10 ? ? ns write data setup time twds 20 ? ? ns write data hold time twdh 10 ? ? ns csb setup time (at read) trcs 10 ? ? ns csb hold time (at read) trch 0 ? ? ns csb setup time (at write) twcs 10 ? ? ns csb hold time (at write) twch 10 ? ? ns wrb pulse width tww 10 ? ? ns fr0b setup time tf0s 3 ? ? ns fr0b output delay time tf0d ? ? 20 ns read data output delay time trdd ? ? 30 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 35 ? ? ns csb disable time tcd cl = 50 pf 10 ? ? ns figure 7 transmit/receive buffer interface (frame mode) a7-a0 input d15-d0 input- output csb input wrb input rdb input write timing read timing twas twah twds twdh twch trdd trcs trdh tww trw a1 d1 input a2 d2 output twcs trch tras trah fr1b output fr0b output tf1s tf1d tf0s tf0d tcd
fedl7204-001digest-01 oki semiconductor ML7204-001 20/42 transmit/receive buffer interface (dma mode) (avdd = 3.0 to 3.6v, dvdd0, 1, 2 = 3.0 to 3.6 v, agnd = dgnd0, 1, 2 = 0.0 v, ta = ?20 to 60 c unless otherwise specified) parameter symbol condition min. typ. max. unit dmarq1b setup time tdr1s 3 ? ? ns tdr1rd ? ? 30 ns dmarq1b output delay time tdr1fd ? ? 30 ns address setup time (at read) tras 10 ? ? ns address hold time (at read)) trah 0 ? ? ns address setup time (at write) twas 10 ? ? ns address hold time (at write) twah 10 ? ? ns write data setup time twds 20 ? ? ns write data hold time twdh 10 ? ? ns ack0b setup time tak0s 10 ? ? ns ack0b hold time tak0h 0 ? ? ns ack1b setup time tak1s 10 ? ? ns ack1b hold time tak1h 10 ? ? ns wrb pulse width tww 10 ? ? ns dmarq0b setup time tdr0s 3 ? ? ns tdr0rd ? ? 30 ns dmarq0b output delay time tdr0fd ? ? 30 ns read data output delay time trdd ? ? 30 ns read data output hold time trdh 3 ? ? ns rdb pulse width trw 35 ? ? ns ackb disable time tad cl = 50 pf 10 ? ? ns figure 8 transmit/receive buffer interface (dma mode) a7-a0 input d15-d0 input- output ack0b input wrb input rdb input write timing read timing twas twah twds twdh trdd tak0s trdh tww trw a1 d1 input a2 d2 output tak0h tras trah dmarq1b output dmarq0b output tdr1s tdr1rd tdr0s tdr0rd ack1b input tak1h tak1s tad tdr1fd tdr0fd
fedl7204-001digest-01 oki semiconductor ML7204-001 21/42 pin functional description ain0n, ain0p, gsx0, ain1n, and gsx1 these are transmit analog input and transmit gain ad justment pins. ain0n and ain1n are connected to inverted input pins of internal transmission amplifiers amp0 and amp1, and ain0p is connected to a noninverting input pin of amp0. gsx0 and gsx1 are connected to output pins of amp0 and amp1. see figure 9 for the gain adjustment. at power down (pdnb = ?0? or spdn = ?1?), outputs of gsx0 and gsx1 are in a high impedance state. when the application does not use amp0, short-circuit gsx0 and ain0n and connect ain0p with avref. when not using amp1, short-circuit gsx1 and ain1n. vfro0 and vfro1 these are receive analog output pins. vfro0 and vfro1 are connected to output pins of amplifiers amp2 and amp3. output of output signals, vfro0 and vfro1, can be selected using the vfro0 selection register (vfro0_sel) and vfro1 selection register (vfro1_sel): when output is selected (?1?), the receive signal is output and when output is not selected (?0?), avref (about 1.4 v) is output. in power down mode, these output pins are set to a high impedance state. it is recommended to use output signals through a dc coupling capacitor. (note) if output selection is changed while the conversation is in progress, a micronoise is ge nerated. therefore, it is recommended to select output before starting a call and then start a call. before canceling reset or resetting, it is recommended to select output of vfro0 and vfro1 to the avref output side. figure 9 analog interface c4 vfro1 10k ? vfro1_sel out : 1.3vp-p max. amp3 d/a1 d/a0 c3 vfro0 10k ? vfro0_sel out : 1.3vp-p max. amp2 vref avref c6 0.1 f c5 2.2 to 4.7 f + r1 r2 ain0n gsx0 10k ? ain0p c1 gain = r2/r1 <= 32(+30db) r1 : variable r2 : 500k max. amp0 a/d0 ain1n gsx1 10k ? r3 r4 c2 gain = r4/r3 <=32(+30db) r3 : variable r4 : 500k max. amp1 a/d1
fedl7204-001digest-01 oki semiconductor ML7204-001 22/42 avref this is an output pin of an analog signal ground potential. with the output potential of about 1.4 v, insert bypass capacitors of 2.2 to 4.7 f (aluminum electrolysis type) and 0.1 f (ceramic type) in parallel. avref outputs 0.0 v at power down. avref starts being powered up after power-down reset, the system restarts from ( pdnb = ?1? and spdn = ?0?). xi and xo these are the master clock input pin (xi) and the crystal connection pins for the master clock (xi and xo). oscillation stops at power down by pdnb or softwa re power down by spdn. oscillation starts after power-down is reset and the clock is supplied to the lsi internal section after oscillation stabilization delay time has elapsed (about 21.3 ms). figure 10 shows a master clock input example. figure 10 example of an osc illation circuit and clock input clkout this is a 12.288 mhz master clock output pin. (provided for 100-pin packages only) since output is disabled in the initial state, set the 12.288 mhz clock output enable control register (clkout_en) to ?1? when clock output is required. pdnb this is a power-down control input pin. a power-down state can be set by setting this pin to ?0?. this pin also functions as an lsi reset pin. to prevent an lsi operation error, use pdnb for the initial power-down reset after power is applied. to put the lsi in to a power-down state, fix pdnb to ?0? for 250 s or more. lsi power-down reset can be performed by setting the software power down reset control register spdn to ?0? ?1? ?0?. power-down is released, the initial mode display regist er (ready) is set to ?1? after 200 ms, and various function setting modes (initial modes) are entered. see figure 1 for the timings of pdnb, avref, xo, and the initial mode. (note) turn on the power in a power-down state by pdnb. when using the lsi by inputting a master clock to the xi pin, first maintain the power-down state (pdnb = 0) until power is applied to the digital power supply (dvd0, 1, and 2) and the analog power supply (avdd) (90% or more) and the master clock is input to the xi pin, then release the power-down state (pdnb = 0 1) . in this case also, fix pdnb to ?0? for 250 s or more. xi xo r crystal c1 c2 12.288 mhz crystal (12.288 mhz) kyocera kinseki corp. hc-49/u-s [c l =12pf] c2 r 8 pf 1 m ? pdnb cr0-b7 (spdn) xi xo open pdnb cr0-b7 (spdn) c1 8 pf to the internal section clkout to the internal section clkout provisional
fedl7204-001digest-01 oki semiconductor ML7204-001 23/42 dvdd0, dvdd1, dvdd2, and avdd these are power supply pins. dvdd0, dvdd1, and dvdd2 are connected to the po wer supply of a digital circuit and avdd is connected to a power supply of an analog circuit. connect these pins near the lsi and insert bypass capacitors of 10 f (electrolysis type) and 0.1 f (ceramic type) between dgnd and agnd in parallel. dgnd0, dgnd1, dgnd2, and agnd these are ground pins. dgnd0, dgnd1, and dgnd2 are c onnected to grounds of di gital circuits and agnd is connected to a ground of an analog circ uit. connect these pins near the lsi. vregout this is an output pin of an internal regulator voltage (about 2.5 v). connect a capacitor of about 0.1 f (ceramic type) in parallel to about 10 f (ceramic or tantalum type) between this pin and a ground pin. vbg this is a reference output pin for an internal regulator. connect a laminated ceramic capacitor of about 150 pf between this pin and a ground pin. tst0 and tst1 these are input pins for testing. at normal use, input ?0?.
fedl7204-001digest-01 oki semiconductor ML7204-001 24/42 intb/gpioa[6] primary function: intb this in an interrupt request output pin. when the interrupt cause is changed, this pin outputs a ?l? level for about 1.0 s. when the interrupt factor is not changed, ?h? is output. the interrupt factor can be checked by reading cr16-cr22. table 1 lists the interrupt causes. the interrupt causes can be masked individually in the internal memory (interrupt cause mask control). table 1 interrupt causes cr bit register name rising edge falling edge remarks b2 fsk receive overrun error notification register (fdet_oer) { b1 fsk receive framing error notification register (fdet_fer) { cr16 b0 fsk receive data read request notification register (fdet_rq) { cr17 b0 fsk output data setting completion flag (fgen_flag) { cr18 b0 timer overflow display register (tmovf) { b7 dsp status register (dsp_err) { b4 tone1 detector detection status register (tone1_det) { { b3 tone0 detector detection status register (tone0_det) { { b2 tgen1 execution flag display register (tgen1_exflag) { { cr19 b1 tgen0 execution flag display register (tgen0_exflag) { { b6 dial pulse detector detection status register (dp_det) { { b4 dtmf detector detection status register (dtmf_det) { { cr20 b3-b0 dtmf code display register (dtmf_code[3:0]) { { b3 ch2 transmit error status register (txerr_ch2) { { b2 ch1 transmit error status register (txerr_ch1) { { b1 ch2 transmit request notification register (fr0_ch2) { cr21 b0 ch1 transmit request notification register (fr0_ch1) { b3 ch2 receive error status register (rxerr_ch2) { { b2 ch1 receive error status register (rxerr_ch1) { { b1 receive invalid write error notification register (rxbw_err) { { cr22 b0 receive request notification register (fr1) { { : with intb interrupt generation function : without intb interrupt generation function secondary function: gpioa[6] when the primary function/secondary function selection register (gpfa[6]) of gpioa[6] is set to ?1?, this pin functions as a general-purpose i/o port gpioa[6].
fedl7204-001digest-01 oki semiconductor ML7204-001 25/42 a0-a7 these are address input pins for accessing a frame/dma /control register. each address is as follows. transmit buffer (tx buffer) a7-a0 = 80h receive buffer (rx buffer) a7-a0 = 81h control register (cr) see tables 5 to 8 for the addresses. d0-d15 these are data i/o pins for accessing a frame/dma/control regi ster. since these pins are i/o pins, connect pull-up resistors. when an 8-bit bus access is selected in the mcu in terface data width se lection register (bw_sel), pins d0-d7 are enabled. when using the pi ns with 8-bit bus access (bw_sel = ?1?), fix the input of high-order d8-d15 to either ?0? or ?1? since they are constantly in an input state. csb this is a chip select input pin for accessing a frame/control register. rdb this is a read enable input pin fo r accessing a frame/dma/control register. wrb this is a write enable input pin for accessing a frame/dma/control register.
fedl7204-001digest-01 oki semiconductor ML7204-001 26/42 fr0b (dmarq0b) ? fr0b (frame/dma selection register fd_sel = ?0? in frame mode) this is a transmit frame output pin that outputs data wh en the transmit buffer for frame access becomes full. when the transmit buffer becomes full, the pin outputs ?l? and retains ?l? until the specified number of words are read from the mcu. ? dmarq0b (frame/dma selection register fd_sel = ?1? in dma mode) this is a dma request output pin that outputs data when the transmit buffer for dma access becomes full. when the transmit buffer becomes full, the pin outputs ?l? and the value is reset to ?h? automatically when an acknowledgment signal (ack0b = ?0?) and the fall of a read enable signal (rdb = ?1? ?0?) are received from the mcu side. this operation is repeated until th e specified number of words are read from the mcu. fr1b (dmarq1b) ? fr1b (frame/dma selection register fd_sel = ?0? in frame mode) this receive frame output pin outputs data when the receive buffer for frame access becomes empty. when the receive buffer becomes empty, the pin outputs ?l? an d retains ?l? until the specifi ed number of words are written from the mcu. ? dmarq1b (frame/dma selection register fd_sel = ?1? in dma mode) this a dma request output pin that outputs data wh en the receive buffer for dma access becomes empty. when the receive buffer becomes empty, the pin outputs ?l? and the value is reset to ?h? automatically when an acknowledgment signal (ack1b = ?0?) and the fall of a write enable signal (wrb = ?1? ?0?) are received from the mcu side. this opeation is repeat ed until the specified numbe r of words are written from the mcu side. ack0b/gpioa[4] primary function: ack0b this is a dma acknowledgment input pin for dmarq0b for transmit buffer dma access; it is enabled in dma mode (fd_sel = ?1?). when using the pin in frame mode (fd_sel = ?0?), fix this pin to ?1?. secondary function: gpioa[4] when the primary function/secondary function registration re gister (gpfa[4]) of gpioa[4] is set to ?1?, the pin functions as a general-purpose i/o port gpioa[4]. ack1b/gpioa[5] primary function: ack0b this is a dma acknowledgment input pin for dmarq1b for receive buffer dma access; it is enabled in dma mode (fd_sel = ?1?). when using this pin in frame mode (fd_sel = ?0?), fix this pin to ?1?. secondary function: gpioa[5] when the primary function/secondary function registration re gister (gpfa[5]) of gpioa[5] is set to ?1?, the pin functions as a general-purpose i/o port gpioa[5]. gpioa[0], gpioa[1], gpioa[2], and gpioa[3] these are general-purpose i/o ports a[3:0]. however, the following secondary functions are assigned to gpioa[0] and gpioa[2]. secondary function of gpioa[0]: input pin (dpi) of a dial pulse detecter (dpdet) secondary function of gpioa[2]: output pin (dpo) of a dial pulse transmitter (dpgen)
fedl7204-001digest-01 oki semiconductor ML7204-001 27/42 gpiob[5:0] this is a general-purpose i/o port b[5:0]. (provided for 100-pin packages only.) gpioc[7:0] this is a general-purpose i/o port c[7:0]. (provided for 100-pin packages only.) clksel this is an input-output control input pin of sync and bclk. the pin controls input when it is set to ?0? and output when it is set to ?1?. sync this is a 8 khz synchronous signal i/o pin of pcm signals. when clksel is ?0?, constantly input an 8 khz clock synchronized with bclk. when clksel is ?1?, this pin outputs an 8 khz clock synchronized with bclk. when the sync frame control register (sync_se l) is ?0?, long frame synchronization is specified and when the register is ?1?, shor t frame synchronization is specified. bclk this is a shift clock i/o pin of a pcm signal. when clksel is ?0?, clock input synchronized with s ync is necessary. when g.711 is selected, input a clock of 64 khz to 2.048 mhz and when 16-bit linear is selected, input a clock of 128 khz to 2.048 mhz. when clksel is ?1?, this pin outputs a clock of 2.048 mhz synchronized with sync. (remarks) table 2 shows the input-output control of sync and bclk and the frequencies. table 2 sync and bclk input-output control clksel sync bclk remarks ?0? input (8 khz) input (64 khz to 2048 khz) always input a clock after start of power supply. when g.711 is selected, input a clock of 64 khz to 2.048 mhz. when 16-bit linear is selected, input a clock of 128 khz to 2.048 mhz. ?1? output (8 khz) output (2.048 mhz) at power down, ?l? is output. pcmo this is a pcm signal output pin. a pcm signal is output synchronized with the rise of bclk or sync. for the output from pcmo, data is output to only the a pplicable time slot section according to the selected coding format and the setting of the time slot position and other sections are set to a high-impedance state. if a pcm interface is not used, pcmo is set to a high impedance state. (note) be sure to connect a pull-up resistor externally to the pcmo pin, because the pin is an open drain output pin. do not use a pull-up voltage greater than the digital power supply voltage (dvdd). pcmi this is a pcm signal input pin. the signal is shifted at falling of bclk and is input from msb. if a pcm interface is not used, fi x the input to ?0? or ?1?.
fedl7204-001digest-01 oki semiconductor ML7204-001 28/42 functional description transmit and receive buffers configuration examples configuration example 1 (basic call, codec_a) this example shows the configuration fo r making calls with an analog tele phone set (a-tel) on the nw side by connecting the analog telephone interface on the linear pcm codec_a side. txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr cente r clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp_det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w ch2 g.711 t s w g.729.a decoder ch1 rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g.711 rxgain _ its2 rxgain_its1 pcm_txen1 txgain_pcm1 rx_sig pcm_txen0 txga in_pcm0 pcm_rxen1 rxgain_pcm1 rxgain pcm0 pcm _ rxen0 rx_sig rxdet rxgain_sc sc_rxen dc_en dc_en rx1t _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/ d) fsk_gen tone_gen0 (tone a/ b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in _ ch1 _ ch2 unused rxgain ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel voip-nw ml7204 (configuration example 1)
fedl7204-001digest-01 oki semiconductor ML7204-001 29/42 configuration example 2 (basic call, codec_b) this example shows the configuration fo r making calls with an analog tele phone set (a-tel) on the nw side by connecting the analog telephone interface on the linear pcm codec_b side. txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx1 10k ? a mp1 linear pcm (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgen txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr cente r clip sin rout sout rin codecb_txen codecb_rxen codeca codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp_det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag rxgain _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w g.711 t s w g.729.a decoder ch1 rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g.711 rxgain_its2 rxgain_its1 pcm_txen1 txga in pcm1 rx_sig pcm_txen0 txga in_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxdet rxgain_s sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone) fsk_gen tone_gen0 (tone) tgen1_exfl tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in txga in _ ch2 unused ch2 ec rx_sig linea r pcm codec (codec_b) linea r pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel voip-nw ml7204 (configuration example 2)
fedl7204-001digest-01 oki semiconductor ML7204-001 30/42 configuration example 3 (callin g using extension with pcm) txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr cente r clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w g.711 t s w g.729.a decoder ch1 rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g.711 rxgain_its2 rxgain_its1 pcm_txen1 txga in_pcm1 rx_sig pcm_txen0 txga in_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxd300et rxgain_s sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/ d) fsk_gen tone_gen0 (tone a/ b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in _ ch1 txga in _ ch2 unused rxgain ch2
fedl7204-001digest-01 oki semiconductor ML7204-001 31/42 this example shows the configuration for making calls using extension between two analog telephone sets (a-tel1 and a-tel2) on the equipment that has two or more analog telephone interface ports. ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel1 ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel2 ml7204 (configuration example 3) ml7204 (configuration example 3)
fedl7204-001digest-01 oki semiconductor ML7204-001 32/42 configuration example 4 (three-way calling: termina l side [two parties] ? nw side [one party]) txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr cente r clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp_det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag rxgain _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w ch2 g.711 t s w g.729.a decoder rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g. 7 11 rxgain_its2 rxgain_its1 pcm_txen1 txga in_pcm1 rx_sig pcm_txen0 txga in_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxdet rxgain_sc sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/d) fsk_gen tone_gen0 (tone a/b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in ch1 txga in _ ch2 unused ch1
fedl7204-001digest-01 oki semiconductor ML7204-001 33/42 this example shows the configuration for making three-way calling between the terminal side (two parties) and the voip nw side (one party). ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel2 ml7204 (configuration example 3) ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel1 ml7204 (configuration example 4) voip-nw
fedl7204-001digest-01 oki semiconductor ML7204-001 34/42 configuration example 5 (three-way calling: termina l side [one party] ? nw side [two parties]) this example shows the configuration for making three- way calling between the terminal side (one party) and voip nw side (two parties). txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr cente r clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_det1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio gpio dp d timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag rxgain _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w g.711 t s w g.729.a decoder ch1 rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g.711 rxgain _ its2 rxgain_its1 pcm_txen1 txga in_pcm1 rx_sig pcm_txen0 txgain_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxdet rxgain_sc sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/d) fsk_gen tone_gen0 (tone a/b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timov timovf tst1 tst0 pdnb clkout txga in txga in _ ch2 unused ch2 ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel ml7204 (configuration example 5) voip-nw1 voip-nw2
fedl7204-001digest-01 oki semiconductor ML7204-001 35/42 configuration example 6 (three-way cal ling: terminal side [three parties]) this example shows the configuration for making thr ee-way calling between analog telephones (a-tel1, a-tel2, and a-tel3) on the equipment with multiple analog telephone interface ports. txga ina rxgainb vfro0 10k ? a mp ain0n gsx0 10k ? ain0p a mp linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? amp3 ain1n gsx]1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad atts attr center clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf_det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controlle r control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp_det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet_rq fgen_flag rxgain _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w ch2 g.711 t s w g.729.a decoder ch1 rxgain _ ch2 pcm i/f ts cont p/s s/p pcm codec encoder g.711 decoder g.711 rxgain_its2 rxgain_its1 pcm_txen1 txgain_pcm1 rx_sig pcm_txen0 txgain_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxdet rxgain_sc sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/ d) fsk_gen tone_gen0 (tone a/ b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in _ ch1 txga in _ ch2 unused ec rx_sig linear pcm codec linear pcm codec speech codec pcm i/f pcm codec mcu i/f rx_sig a -tel2 a -tel1 a -tel3 ec rx_sig linear pcm codec (codec_b) linear pcm codec speech codec pcm i/f pcm codec mcu i/f rx_sig ec rx_sig linear pcm codec linear pcm codec speech codec pcm i/f pcm codec mcu i/f rx_sig ml7204 (configuration example 6) ml7204 (configuration example 6) ml7204 (configuration example 6) (codec_a) (codec_b) (codec_a) (codec_b) (codec_a)
fedl7204-001digest-01 oki semiconductor ML7204-001 36/42 configuration example 7 (codec -a-codec-b loop back mode) this example shows the configura tion where codec_a and codec_b are connected in loopback mode according to the internal path settings. txga ina rxgainb vfro0 10k ? amp2 ain0n gsx0 10k ? ain0p amp0 linear pcm codec (codec_a) d/a0 lpf a/d0 bpf stgaina rxgaina vfro1 10k ? a mp3 ain1n gsx1 10k ? amp1 linear pcm codec (codec_b) d/a1 lpf a/d1 bpf stgainb txga inb rxgena txde ta power dvdd2 dgnd2 agnd dvdd1 dgnd1 dvdd0 dgnd0 avdd vregout vgb vref avref sync (8 khz) osc 12.288 mhz pll xi xo ckgn mck txde tb rxgenb echo canceller + - aff lpad gpad a tts attr center clip sin rout sout rin codecb_txen codecb_rxen codeca_rxen codeca_txen lpen0 lpen1 detector path setting dtmf_rec dtmf_code[3:0] dtmf det fsk_det fdet_d[7:0] fdet_rq fdet_fer/fdet_oer txde ta txde tb tone_de t0 tone0_det tone_de t1 tone1_det rxdet txga in_sc txgen sc_txen tx buffer0 rx buffer0 bus control unit tx buffer1 rx buffer1 a0-a7 8b d0-d15 16b csb rdb wrb fr0b fr1b frame/dma controller control register int sync clksel bclk pcmo pcmi dpgen dpdet gpio0 gpio2 dp_det timer fdet_fer/fdet_oer dtmf_det tone0_det tone1_det dp_det dtmf_code[3:0] fdet rq fgen_flag rxgain _ ch1 speech codec g.729.a g.711 encoder ch1 ch2 t s w ch2 g.711 t s w g.729.a decode ch1 rxgain ch2 pcm i/f ts cont p/s s/p pcm codec encoder g. 7 11 decoder g.711 rxgain_its2 rxgain_its1 pcm_txen1 txga in_pcm1 rx_sig pcm_txen0 txgain_pcm0 pcm_rxen1 rxgain_pcm1 rxgain_pcm0 pcm_rxen0 rx_sig rxdet rxgain sc sc_rxen dc_en dc_en rx1tx2 _ gain rx2tx1 _ gain rxgen generator path tone_gen1 (tone c/ d) fsk_gen tone_gen0 (tone a/ b) tgen1_exflag tgen0_exflag fgen_flag rxgen txgen rxgena rxgenb rxgena_en rxgenb_en gpioc [7:0] gpiob [5:0] gpioa [3:0] 4 6 8 intb/ gpioa[6] ack0b/ gpioa[4] ack1b/ gpioa[5] timovf timovf tst1 tst0 pdnb clkout txga in _ ch1 txga in _ ch2 unused a ec rx_sig linear pcm codec (codec_b) linear pcm codec (codec_a) speech codec pcm i/f pcm codec mcu i/f rx_sig ml7204 (configuration example 7) b
fedl7204-001digest-01 oki semiconductor ML7204-001 37/42 application circuits a vref vfro0 vfro1 50 51 52 53 54 55 56 57 60 61 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xi xo a in1n gsx1 a in0p a in0n gsx0 5 6 8 9 10 11 12 13 14 15 bclk sync rdb wrb csb fr0b fr1b intb a ck0b a ck1b 48 47 46 45 43 42 41 40 39 38 37 36 35 34 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gpioa[0] gpioa[1] gpioa[2] gpioa[3] pdnb clksel d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 +3.3 v +3.3 v +3.3 v power-down control mcu i/f general-purpose i/o pins 12.288 mhz crystal a nalog input pcm i/f a nalog output conditions ? frame mode ? sync and bclk: configured to be output (clksel = "1") 1.4 v 49 a vdd 58 59 62 dgnd2 dvdd2 a gnd 7 dgnd0 dvdd0 44 33 dgnd1 dvdd1 16 1 2 tst1 tst0 vbg vregout 64 63 3 pcmo 4 pcmi +3.3 v ML7204-001ga 500 ? 150pf 10uf 0.1uf 10uf 0.1uf 0.1uf 2.2uf 8pf 8pf 1m ?
fedl7204-001digest-01 oki semiconductor ML7204-001 38/42 a vref vfro0 vfro1 85 86 87 49 48 46 45 43 42 40 39 37 36 34 33 31 30 28 27 15 16 19 20 21 22 23 24 rdb wrb csb fr0b fr1b intb a ck0b a ck1b 75 74 71 70 60 59 58 57 56 55 54 53 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 gpioa[0] gpioa[1] gpioa[2] gpioa[3] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 +3.3 v mcu i/f general-purpose i/o pins a a nalog output vbg vregout 99 98 clksel 66 65 63 62 gpiob[0] gpiob[1] gpiob[2] gpiob[3] 69 68 gpiob[4] gpiob[5] 11 10 5 4 gpioc[0] gpioc[1] gpioc[2] gpioc[3] 78 79 80 82 83 a in1n gsx1 a in0p a in0n gsx0 a nalog input 1.4 v 18 17 14 13 gpioc[4] gpioc[5] gpioc[6] gpioc[7] general-purpose i/o pins b general-purpose i/o pins c 61 pdnb power-down control clkout 1 12.288 mhz clock output conditions ? frame mode ? sync and bclk: configured to be output (clksel = "1") 2 3 tst1 tst0 92 94 xi xo 12.288 mhz crystal +3.3 v 76 a vdd 88 91 95 dgnd2 dvdd2 a gnd 12 dgnd0 dvdd0 67 52 dgnd1 dvdd1 25 8 9 bclk sync 64 +3.3 v pcm i/f 6 pcmo 7 pcmi +3.3 v ML7204-001tb 150 pf 10 ? 500 ? 0.1
fedl7204-001digest-01 oki semiconductor ML7204-001 39/42 package dimensions notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl7204-001digest-01 oki semiconductor ML7204-001 40/42 tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl7204-001digest-01 oki semiconductor ML7204-001 41/42 revision history page document no. date previous edition current edition description fedl7204-001digest-01 aug. 12, 2004 ? ? final edition 1
fedl7204-001digest-01 oki semiconductor ML7204-001 42/42 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circ uit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to , operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically authorized by oki, authorized for use in any system or application that requires special or enha nced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

▲Up To Search▲

Price & Availability of ML7204-001

	To Download ML7204-001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .